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features applications description ADS8505 slas180b ? september 2005 ? revised june 2007 16-bit 250-ksps sampling cmos analog-to-digital converter industrial process control 105db sfdr at 250-khz sample rate data acquisition systems standard 10-v input range digital signal processing 1.5 lsb max inl medical equipment 1 lsb max dnl, 16-bits no missing codes instrumentation 2 mv max bipolar zero error with 0.4 ppm/ c drift 0.1% fsr max full-scale error with 2 the ADS8505 is a complete 16-bit sampling a/d ppm/ c drift converter using state-of-the-art cmos structures. it single 5-v supply operation contains a complete 16-bit, capacitor-based, sar pin-compatible with ads7805 (low speed) a/d with s/h, reference, clock, interface for and 12-bit ads8504/7804 microprocessor use, and 3-state output drivers. uses internal or external reference the ADS8505 is specified at a 250-khz sampling full parallel data output rate over the full temperature range. precision resistors provide an industry standard 10-v input 70-mw typ power dissipation at 250 ksps range, while the innovative design allows operation 28-pin ssop and soic packages from a single +5-v supply, with power dissipation under 100 mw. the ADS8505 is available in 28-pin soic and 28-pin ssop packages, both fully specified for operation over the industrial ?40 c to 85 c temperature range. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2005?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
successive approximation register and control logic clock busy comparator byte cs r/c cdac buffer ref cap 10 v input 5 k 2 k 9.8 k internal +2.5 v ref 4 k output latches and three state drivers three state parallel data bus
absolute maximum ratings (1) electrical characteristics ADS8505 slas180b ? september 2005 ? revised june 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. package/ordering information (1) minimum no minimum specification relative package package ordering transport product missing sinad temperature accuracy lead designator number media, qty code (db) range (lsb) ADS8505ibdw tube, 20 so-28 dw ADS8505ibdwr tape and reel, 1000 ADS8505ib 1.5 16 86 ?40 c to 85 c ADS8505ibdb tube, 50 ssop-28 db ADS8505ibdbr tape and reel, 2000 ADS8505idw tube, 20 so-28 dw ADS8505idwr tape and reel, 1000 ADS8505i 4 15 83 ?40 c to 85 c ADS8505idb tube, 50 ssop-28 db ADS8505idbr tape and reel, 2000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com. over operating free-air temperature range (unless otherwise noted) (2) unit v in 25v analog inputs ref +v ana + 0.3 v to agnd2 ? 0.3 v cap indefinite short to agnd2, momentary short to v ana dgnd, agnd1, agnd2 0.3 v v ana 6 v ground voltage differences v dig to v ana 0.3 v v dig 6 v digital inputs ?0.3 v to +v dig + 0.3 v maximum junction temperature 165 c internal power dissipation 825 mw lead temperature (soldering, 10s) 300 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. t a = ?40 c to 85 c, f s = 250 khz, v dig = v ana = 5 v, using internal reference (unless otherwise noted) ADS8505i ADS8505ib parameter test conditions unit min typ max min typ max resolution 16 16 bits analog input voltage range 10 10 v impedance 11.5 11.5 k w capacitance 50 50 pf throughput speed conversion cycle acquire and convert 4 4 m s throughput rate 250 250 khz 2 submit documentation feedback www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 electrical characteristics (continued) t a = ?40 c to 85 c, f s = 250 khz, v dig = v ana = 5 v, using internal reference (unless otherwise noted) ADS8505i ADS8505ib parameter test conditions unit min typ max min typ max dc accuracy inl integral linearity error ?4 4 ?1.5 1.5 lsb (1) dnl differentiall linearity error ?2 2 ?1 1 lsb (1) no missing codes 15 16 bits transition noise (2) 0.77 0.77 lsb full-scale error (3) (4) int. ref. ?0.5 0.5 ?0.25 0.25 %fsr full-scale error drift int. ref. 7 7 ppm/ c full-scale error (3) (4) ext. 2.5-v ref. ?0.25 0.25 ?0.1 0.01 0.1 %fsr full-scale error drift ext. 2.5-v ref. 2 2 ppm/ c bipolar zero error (3) ?5 5 ?2 2 mv bipolar zero error drift 0.4 0.4 ppm/ c power supply sensitivity ?8 8 ?8 8 +4.75 v < v d < +5.25 v lsb (v dig = v ana = v d ) ac accuracy sfdr spurious free dynamic range f i = 20 khz 92 98 96 105 db (5) thd total harmonic distortion f i = 20 khz ?98 ?92 ?103 ?96 db f i = 20 khz 83 88 86 88 db sinad signal-to-(noise + distortion) ?60-db input 30 32 db snr signal-to-noise ratio f i = 20 khz 83 88 86 88 db full-power bandwidth (6) 500 500 khz sampling dynamics aperture delay 5 5 ns transient response fs step 2 2 m s overvoltage recovery (7) 150 150 ns reference internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current (must 1 1 m a use external buffer) internal reference drift 8 8 ppm/ c external reference voltage range for 2.3 2.5 2.7 2.3 2.5 2.7 v specified linearity external reference current drain ext. 2.5-v ref. 100 100 m a digital inputs logic levels v il low-level input voltage ?0.3 0.8 ?0.3 0.8 v v ih high-level input voltage 2.0 v dig +0.3 v 2.0 v dig +0.3 v v i il low-level input current 10 10 m a i ih high-level input current 10 10 m a digital outputs data format (parallel 16-bits) data coding (binary 2's complement) v ol low-level output voltage i sink = 1.6 ma 0.4 0.4 v v oh high-level output voltage i source = 500 ma 4 4 v hi-z state, leakage current 5 5 m a v out = 0 v to v dig output capacitance hi-z state 15 15 pf (1) lsb means least significant bit. for the 16-bit, 10-v input ADS8505, one lsb is 305 m v. (2) typical rms noise at worst case transitions and temperatures. (3) as measured with fixed resistors shown in figure 27 . adjustable to zero with external potentiometer. (4) full-scale error is the worst case of ?full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) all specifications in db are referred to a full-scale 10-v input. (6) full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 db, or 10 bits of accuracy. (7) recovers to specified performance after 2 x fs input overvoltage. 3 submit documentation feedback www.ti.com
device information ADS8505 slas180b ? september 2005 ? revised june 2007 electrical characteristics (continued) t a = ?40 c to 85 c, f s = 250 khz, v dig = v ana = 5 v, using internal reference (unless otherwise noted) ADS8505i ADS8505ib parameter test conditions unit min typ max min typ max digital timing bus access timing 83 83 ns bus relinquish timing 83 83 ns power supplies v dig digital input voltage 4.75 5 5.25 4.75 5 5.25 v v ana analog input voltage 4.75 5 5.25 4.75 5 5.25 v must be v ana i dig digital input current 2 5 2 5 ma i ana analog input current 12 15 12 15 ma power dissipation f s = 250 khz 70 100 70 100 mw temperature range specified performance ?40 85 ?40 85 c derated performance (8) ?55 125 ?55 125 c storage ?65 150 ?65 150 c thermal resistance ( q ja ) ssop 62 62 c/w so 46 46 c/w (8) the internal reference may not be started correctly beyond the industrial temperature range (?40 c to 85 c), therefore use of an external reference is recommended. db or dw package (top view) 4 submit documentation feedback www.ti.com v dig v ana busycs r/c byte d0 (lsb) d1 d2 d3 d4 d5 d6 d7 v in agnd1 ref cap agnd2 d15 (msb) d14d13 d12 d11 d10 d9d8 dgnd 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15
ADS8505 slas180b ? september 2005 ? revised june 2007 device information (continued) terminal functions terminal digital description i/o name db/dw no. agnd1 2 analog ground. used internally as ground reference point. agnd2 5 analog ground. busy 26 o at the start of a conversion, busy goes low and stays low until the conversion is completed and the digital outputs have been updated. byte 23 i selects 8 most significant bits (low) or 8 least significant bits (high). cap 4 reference buffer capacitor. 2.2- m f tantalum capacitor to ground. cs 25 i internally ored with r/ c. if r/ c is low, a falling edge on cs initiates a new conversion. dgnd 14 digital ground. d15 (msb) 6 o data bit 15. most significant bit (msb) of conversion results. hi-z state when cs is high, or when r/ c is low. d14 7 o data bit 14. hi-z state when cs is high, or when r/ c is low. d13 8 o data bit 13. hi-z state when cs is high, or when r/ c is low. d12 9 o data bit 12. hi-z state when cs is high, or when r/ c is low. d11 10 o data bit 11. hi-z state when cs is high, or when r/ c is low. d10 11 o data bit 10. hi-z state when cs is high, or when r/ c is low. d9 12 o data bit 9. hi-z state when cs is high, or when r/ c is low. d8 13 o data bit 8. hi-z state when cs is high, or when r/ c is low. d7 15 o data bit 7. hi-z state when cs is high, or when r/ c is low. d6 16 o data bit 6. hi-z state when cs is high, or when r/ c is low. d5 17 o data bit 5. hi-z state when cs is high, or when r/ c is low. d4 18 o data bit 4. hi-z state when cs is high, or when r/ c is low. d3 19 o data bit 3. hi-z state when cs is high, or when r/ c is low. d2 20 o data bit 2. hi-z state when cs is high, or when r/ c is low. d1 21 o data bit 1. hi-z state when cs is high, or when r/ c is low. d0 (lsb) 22 o data bit 0. least significant bit (lsb) of conversion results. hi-z state when cs is high, or when r/ c is low. r/ c 24 i with cs low and busy high, a falling edge on r/ c initiates a new conversion. with cs low, a rising edge on r/ c enables the parallel output. ref 3 reference input/output. 2.2- m f tantalum capacitor to ground. v ana 27 analog supply input. nominally +5 v. decouple to ground with 0.1- m f ceramic and 10- m f tantalum capacitors. v dig 28 digital supply input. nominally +5 v. connect directly to pin 27. must be v ana . v in 1 analog input. see figure 28 . 5 submit documentation feedback www.ti.com
typical characteristics ADS8505 slas180b ? september 2005 ? revised june 2007 spurious free dynamic range total harmonic distortion signal-to-noise ratio vs vs vs free-air temperature free-air temperature free-air temperature figure 1. figure 2. figure 3. signal-to-noise signal-to-noise and distortion signal-to-noise ratio and distortion vs vs vs free-air temperature input frequency input frequency figure 4. figure 5. figure 6. spurious free dynamic range total harmonic distortion internal reference voltage vs vs vs input frequency input frequency free-air temperature figure 7. figure 8. figure 9. 6 submit documentation feedback 70 75 80 85 90 95 100 -40 -20 0 20 40 60 80 t - free-air temperature - c a o snr - signal-to-noise ratio - db f = 250 ksps f = 20 khz si 70 75 80 85 90 95 100 -40 -20 0 20 40 60 80 t - free-air temperature - c a o sinad - signal-to-noise and distortion - db f = 250 ksps f = 20 khz si 70 75 80 85 90 95 100 1 10 100 125 f - input frequency - khz i snr - signal-to-noise ratio - db www.ti.com 60 65 70 75 80 85 90 95 100 105 1 10 100 125 f - input frequency - khz i sinad - signal-to-noise and distortion - db 2.490 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 ?40 ?20 0 20 40 60 80 internal reference v oltage ? v t a ? free-air t emperature ? c -105-100 -95-90 -85 -80 -75 -40 -20 0 20 40 60 80 t - free-air temperature - c a o thd - t otal harmonic distortion - db f = 250 ksps f = 20 khz si 60 70 80 90 100 110 120 1 10 100 125 f - input frequency - khz i thd - total harmonic distortion - db 80 85 90 95 100 105 110 -40 -20 0 20 40 60 80 t - free-air temperature - c a o sfdr - spurious free dynamic range - db f = 250 ksps, f = 20 khz si 75 85 95 105 115 1 10 100 125 f - input frequency - khz i sfdr - spurious free dynamic range - db 80 90 110 100 120
ADS8505 slas180b ? september 2005 ? revised june 2007 typical characteristics (continued) bipolar zero scale error negative full-scale error negative full-scale error vs vs vs free-air temperature free-air temperature free-air temperature figure 10. figure 11. figure 12. positive full-scale error positive full-scale error supply current vs vs vs free-air temperature free-air temperature free-air temperature figure 13. figure 14. figure 15. performance vs histogram cap pin capacitor esr figure 16. figure 17. 7 submit documentation feedback ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 ?40 ?20 0 20 40 60 80 negative full?scale error ? %fsr t a ? free-air t emperature ? c internal reference ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 ?40 ?20 0 20 40 60 80 negative full?scale error ? %fsr t a ? free-air t emperature ? c external reference ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?40 ?20 0 20 40 60 80 bpz ? bipolar zero scale error ? mv t a ? free-air t emperature ? c ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 ?40 ?20 0 20 40 60 80 positive full?scale error ? %fsr t a ? free-air t emperature ? c internal reference ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 ?40 ?20 0 20 40 60 80 positive full?scale error ? %fsr t a ? free-air t emperature ? c external reference 10 11 12 13 14 15 16 17 18 19 20 -40 -20 0 20 40 60 80 t - free-air temperature - c a o i - supply current - ma d d www.ti.com 1 151 2221 4028 1713 76 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 ?3 ?2 ?1 0 1 2 3 8192conversions of a dc input hits code 50 60 70 80 90 100 110 0 1 2 3 4 5 6 7 8 9 10 esr - resistance - w performance | thd | sinad 2.2 f capacitor on cap pin (pin 4) m
basic operation ADS8505 slas180b ? september 2005 ? revised june 2007 typical characteristics (continued) integral nonlinearity figure 18. differential nonlinearity figure 19. fft (20-khz input) figure 20. figure 21 shows a basic circuit to operate the ADS8505 with a full parallel data output. taking r/ c (pin 24) low for a minimum of 40 ns (1.75 m s max) initiates a conversion. busy (pin 26) goes low and stays low until the conversion is completed and the output registers are updated. data is output in binary 2's complement format with the msb on pin 6. busy going high can be used to latch the data. 8 submit documentation feedback www.ti.com -1.5 -1 -0.5 0 0.5 1 1.5 0 16384 32768 49152 65536 code inl - lsbs -1 -0.5 0 0.5 1 0 16384 32768 49152 65536 code dnl - lsbs -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 25 50 75 100 125 f - frequency - khz amplitude - db 8192 pointsf s = 250 ksps f i = 20 khz, 0db sinad = 87.7 dbthd = -103.9 db
starting a conversion ADS8505 slas180b ? september 2005 ? revised june 2007 basic operation (continued) the ADS8505 begins tracking the input signal at the end of the conversion. allowing 4 m s between convert commands assures accurate acquisition of a new signal. the offset and gain are adjusted internally to allow external trimming with a single supply. the external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the calibration section). the combination of cs (pin 25) and r/ c (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of the ADS8505 in the hold state and starts conversion n. busy (pin 26) goes low and stays low until conversion n is completed and the internal output register has been updated. all new convert commands during busy low will abort the conversion in progress and reset the adc (see figure 26 ). the ADS8505 begins tracking the input signal at the end of the conversion. allowing 4 m s between convert commands assures accurate acquisition of a new signal. refer to table 1 for a summary of cs, r/ c, and busy states and figure 23 through figure 25 for the timing diagrams. cs and r/ c are internally ored and level triggered. there is not a requirement which input goes low first when initiating a conversion. if, however, it is critical that cs or r/ c initiates conversion n, be sure the less critical input is low at least 10 ns prior to the initiating input. to reduce the number of control pins, cs can be tied low using r/ c to control the read and convert modes. the parallel output becomes active whenever r/ c goes high. refer to the reading data section. table 1. control line functions for read and convert cs r/ c busy operation 1 x x none. databus is in hi-z state. 0 1 initiates conversion n. databus remains in hi-z state. 0 1 initiates conversion n. databus enters hi-z state. 0 1 - conversion n completed. valid data from conversion n on the databus. 1 1 enables databus with valid data from conversion n. 1 0 enables databus with valid data from conversion n-1 (1) . conversion n in progress. 0 - 0 enables databus with valid data from conversion n-1 (1) . conversion n in progress. 0 0 - data is invalid. cs and/or r/ c must be high when busy goes high. x 0 conversion n is halted. causes adc to reset. (2) (1) see figure 23 and figure 24 for constraints on data valid from conversion n-1. (2) see figure 26 for details on adc reset. 9 submit documentation feedback www.ti.com
reading data parallel output (after a conversion) parallel output (during a conversion) ADS8505 slas180b ? september 2005 ? revised june 2007 figure 21. basic operation the ADS8505 outputs full or byte-reading parallel data in binary 2's complement data output format. the parallel output is active when r/ c (pin 24) is high and cs (pin 25) is low. any other combination of cs and r/ c 3-states the parallel output. valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. byte (pin 23) can be toggled to read both bytes within one conversion cycle. refer to table 2 for ideal output codes and figure 22 for bit locations relative to the state of byte. table 2. ideal input voltages and output codes digital output binary 2's complement description analog input binary code hex code full-scale range 10 v least significant bit (lsb) 305 m v full scale (10 v-1 lsb) 9.999695 v 0111 1111 1111 1111 7fff midscale 0 v 0000 0000 0000 0000 0000 one lsb below midscale -305 m v 1111 1111 1111 1111 ffff ?full scale -10 v 1000 0000 0000 0000 8000 after conversion n is completed and the output registers have been updated, busy (pin 26) goes high. valid data from conversion n is available on d15-d0 (pins 6-13 and 15-22). busy going high can be used to latch the data. refer to table 3 , figure 23 , figure 24 , and figure 25 for timing specifications. after conversion n has been initiated, valid data from conversion n-1 can be read and is valid up to t 2 (2.2 m s typ) after the start of conversion n. do not attempt to read data from t 2 (2.2 m s typ) after the start of conversion n until busy (pin 26) goes high; this may result in reading invalid data. refer to table 3 , figure 23 , figure 24 , and figure 25 for timing specifications. note: for the best possible performance, data should not be read during a conversion. the switching noise of the asynchronous data transfer can cause digital feedthrough degrading converter performance. 10 submit documentation feedback 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 ADS8505 +5v + + + + convert pulse 40 ns min 200 w 2.2 m f 2.2 m f 0.1 m f 10 m f 33.2 k w b15 (msb) b14b13 b12 b11 b10 b9b8 b0 (lsb)b1 b2 b3 b4 b5 b6 b7 www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 the number of control lines can be reduced by tying cs low while using the falling edge of r/ c to initiate conversions and the rising edge of r/ c to activate the output mode of the converter. see figure 23 . table 3. conversion timing symbol description min typ max units t w1 pulse duration, convert 40 1750 ns t a access time, data valid after r/ c low 2.2 3.2 m s t pd propagation delay time, busy from r/ c low 15 25 ns t w2 pulse duration, busy low 2.2 m s t d1 delay time, busy after end of conversion 5 ns t d2 delay time, aperture 5 ns t conv conversion time 2.2 m s t acq acquisition time 1.8 m s t dis disable time, bus 10 30 83 ns t d3 delay time, busy after data valid 35 50 ns t v valid time, previous data remains valid after r/ c low 1.5 2 m s t conv + t acq throughput time 4 m s t su setup time, r/ c to cs 10 ns t c cycle time between conversions 4 m s t en enable time, bus 10 30 83 ns t d4 delay time, byte 5 10 30 ns figure 22. bit locations relative to state of byte (pin 23) 11 submit documentation feedback bit 0 (lsb)bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 15 (msb) bit 14bit 13 bit 12 bit 1 1 bit 10 bit 9bit 8 67 8 9 10 11 12 13 14 2322 21 20 19 18 17 16 15 ADS8505 byte low bit 8bit 9 bit 10 bit 1 1 bit 12bit 13 bit 14 bit 15 (msb) bit 7bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 67 8 9 10 11 12 13 14 2322 21 20 19 18 17 16 15 ADS8505 byte high +5 v www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 figure 23. conversion timing with outputs enabled after conversion ( cs tied low) figure 24. using cs to control conversion and read timing figure 25. using cs and byte to control data bus 12 submit documentation feedback busy r/c mode acquire convert convert data bus previous data v alid hi?z data v alid hi?z previous data v alid not v alid acquire data v alid t w1 t c t a1 t w2 t pd t d2 t d1 t conv t acq t dis t v t d3 hi?z state busy r/c data bus mode acquire data v alid hi?z state convert acquire cs t su t su t su t su t w1 t pd t w2 t d2 t conv t en t dis hi?z high byte low byte hi?z hi?z low byte high byte hi?z pins 6 ? 13 pins 15 ? 22 byte cs r/c t su t su t en t d4 t dis www.ti.com
adc reset input ranges ADS8505 slas180b ? september 2005 ? revised june 2007 figure 26. adc reset the adc reset function of the ADS8505 can be used to terminate the current conversion cycle. bringing r/ c low for at least 40 ns while busy is low will initiate the adc reset. to initiate a new conversion, r/ c must return to the high state and remain high long enough to acquire a new sample (see table 3 , t c ) before going low to initiate the next conversion sequence. in applications that do not monitor the busy signal, it is recommended that the adc reset function be implemented as part of a system initialization sequence. the ADS8505 offers a standard 10-v input range. figure 28 shows the necessary circuit connections for the ADS8505 with and without hardware trim. offset and full-scale error specifications are tested and specified with the fixed resistors shown in figure 28 (b). full-scale error includes offset and gain errors measured at both +fs and ?fs. adjustments for offset and gain are described in the calibration section of this data sheet. offset and gain are adjusted internally to allow external trimming with a single supply. the external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the calibration section). the nominal input impedance of 11.5 k w results from the combination of the internal resistor network shown on the front page of the product data sheet and the external resistors. the input resistor divider network provides inherent overvoltage protection assured to at least 25 v. the 1% resistors used for the external circuitry do not compromise the accuracy or drift of the converter. they have little influence relative to the internal resistors, and tighter tolerances are not required. the input signal must be referenced to agnd1. this minimizes the ground loop problem typical to analog designs. the analog signal should be driven by a low impedance source. a typical driving circuit using an opa627 or opa132 is shown in figure 27 . 13 submit documentation feedback r/c busy 4.75v vana 0 ns min t pd t w1 t pd t w1 t c data bus hi-z not valid hi-z not valid data valid t d3 unknown vdig www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 figure 27. typical driving circuit ( 10 v, no trim) 14 submit documentation feedback www.ti.com opa 627 gnd gnd gnd gnd pin 1 pin 7 ? pin 2 + pin3 pin4 pin 6 ?15 v +15 v vin 2.2 f 100 nf 2 k 22 pf 2 k 22 pf 200 33.2 k 2.2 f 2.2 f 100 nf 2.2 f vin agnd1 refcap ADS8505 opa 132 or agnd2 dgnd gnd gnd
application information calibration hardware calibration software calibration no calibration reference ref ADS8505 slas180b ? september 2005 ? revised june 2007 the ADS8505 can be trimmed in hardware or software. the offset should be trimmed before the gain since the offset directly affects the gain. to achieve optimum performance, several iterations may be required. to calibrate the offset and gain of the ADS8505, install the proper resistors and potentiometers as shown in figure 28 (a). to calibrate the offset and gain of the ADS8505 in software, no external resistors are required. see the no calibration section for details on the effects of the external resistors. see figure 28 (b) for circuit connections. the external resistors shown in figure 28 (b) may not be necessary in some applications. these resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. figure 28. circuit diagram with and without external resistors the ADS8505 can operate with its internal 2.5-v reference or an external reference. by applying an external reference to pin 5, the internal reference can be bypassed. the reference voltage at ref is buffered internally with the output on cap (pin 4). the internal reference has an 8 ppm/ c drift (typical) and accounts for approximately 20% of the full-scale error (fse = 0.5%). ref (pin 3) is an input for an external reference or the output for the internal 2.5-v reference. a 2.2- m f capacitor should be connected as close to the ref pin as possible. the capacitor and the output resistance of ref create a low-pass filter to bandlimit noise on the reference. using a smaller value capacitor introduces more noise to the reference degrading the snr and sinad. the ref pin should not be used to drive external ac or dc loads. the range for the external reference is 2.3 v to 2.7 v and determines the actual lsb size. increasing the reference voltage increases the full-scale range and the lsb size of the converter which can improve the snr. 15 submit documentation feedback www.ti.com 12 3 4 5 agnd2 cap ref agnd1 v in + +5 v + gain offset 12 3 4 5 agnd2 cap ref agnd1 v in + + 10 v 200 w 33.2 k w 50 k w 50 k w 2.2 m f 2.2 m f 2.2 m f 2.2 m f 200 w 33.2 k w 10 v (a) 10 v with hardware t rim (b) 10 v without hardware t rim note: use 1% metal film resistors. 576 k w
cap layout power grounding signal conditioning intermediate latches ADS8505 slas180b ? september 2005 ? revised june 2007 application information (continued) cap (pin 4) is the output of the internal reference buffer. a 2.2- m f capacitor can be placed between the cap pin and ground. because the internal reference buffer is internally compensated, the external capacitor is not necessary for compensation of the reference buffer. this relaxes the performance requirements of the capacitor and makes the performance of the adc less sensitive to the capacitor. the output of the buffer is capable of driving up to 2 ma of current to a dc load. a dc load requiring more than 2 ma of current from the cap pin begins to degrade the linearity of the ADS8505. using an external buffer allows the internal reference to be used for larger dc loads and ac loads. do not attempt to directly drive an ac load with the output voltage on cap. this causes performance degradation of the converter. for optimum performance, tie the analog and digital power pins to the same +5-v power supply and tie the analog and digital grounds together. as noted in the electrical specifications, the ADS8505 uses 90% of its power for the analog circuitry. the ADS8505 should be considered as an analog component. the +5-v power for the a/d should be separate from the +5 v used for the system's digital logic. connecting v dig (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. for best performance, the +5-v supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. if +12-v or +15-v supplies are present, a simple +5-v regulator can be used. although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. either using a filtered digital supply or a regulated analog supply, both v dig and v ana should be tied to the same +5-v source. three ground pins are present on the ADS8505. dgnd is the digital supply ground. agnd2 is the analog supply ground. agnd1 is the ground which all analog signals internal to the a/d are referenced. agnd1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. all the ground pins of the a/d should be tied to the analog ground plane, separated from the system's digital logic ground, to achieve optimum performance. both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. this helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. the fet switches used for the sample/hold on many cmos a/d converters release a significant amount of charge injection which can cause the driving op-amp to oscillate. the fet switch on the ADS8505, compared to the fet switches on other cmos a/d converters, releases 5% to 10% of the charge. there is also a resistive front end which attenuates any charge which is released. the end result is a minimal requirement for the anti-alias filter on the front end. any op-amp sufficient for the signal in an application is sufficient to drive the ADS8505. the resistive front end of the ADS8505 also provides an assured 25-v overvoltage protection. in most cases, this eliminates the need for external input protection circuitry. the ADS8505 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus is to be active during conversions. if the bus is not active during conversion, the 3-state outputs can be used to isolate the a/d from other peripherals on the same bus. the 3-state outputs can also be used when the a/d is the only peripheral on the data bus. 16 submit documentation feedback www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 intermediate latches are beneficial on any monolithic a/d converter. the ADS8505 has an internal lsb size of 38 m v. transients from fast switching signals on the parallel port, even when the a/d is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. 17 submit documentation feedback www.ti.com
ADS8505 slas180b ? september 2005 ? revised june 2007 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (september, 2005) to a revision ............................................................................................. page added sfdr value ............................................................................................................................................................... 1 changed 3.0 to 1.5 max inl ................................................................................................................................................. 1 changed 3.0 to 1.5 minimum relative accuracy .................................................................................................................. 2 changed ref and cap - reversed ...................................................................................................................................... 2 changed inl, sfdr, thd, snr values .............................................................................................................................. 2 changed sfdr-ta, thd-ta, sinad-ta, snr-fi, sinad-fi sfdr-fi, thd-fi, idd-ta, cap esr, inl, dnl, and fft curves ............................................................................................................................................................................ 6 changed cap description................................................................................................................................................... 16 changes from a revision (october, 2006) to b revision ............................................................................................. page deleted text from basic operation description ...................................................................................................................... 8 changed text in starting a conversion description ................................................................................................................ 9 changed operation descriptions and r/ c in table ................................................................................................................ 9 added sar reset timing .................................................................................................................................................... 13 added adc reset section ............................................................................................................................................... 13 18 submit documentation feedback www.ti.com
package option addendum www.ti.com 9-aug-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) device marking (4/5) samples ADS8505ibdb active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdbg4 active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdbr active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdbrg4 active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdw active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdwg4 active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdwr active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505ibdwrg4 active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i b ADS8505idb active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i ADS8505idbg4 active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i ADS8505idbr active ssop db 28 tbd call ti call ti -40 to 85 ADS8505i ADS8505idbrg4 active ssop db 28 tbd call ti call ti -40 to 85 ADS8505i ADS8505idw active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i ADS8505idwg4 active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i ADS8505idwr active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i ADS8505idwrg4 active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ADS8505i (1) the marketing status values are defined as follows: active: product device recommended for new designs.
package option addendum www.ti.com 9-aug-2013 addendum-page 2 lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS8505ibdbr ssop db 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 q1 ADS8505ibdwr soic dw 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 q1 ADS8505idwr soic dw 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 q1 package materials information www.ti.com 12-aug-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS8505ibdbr ssop db 28 2000 367.0 367.0 38.0 ADS8505ibdwr soic dw 28 1000 367.0 367.0 55.0 ADS8505idwr soic dw 28 1000 367.0 367.0 55.0 package materials information www.ti.com 12-aug-2013 pack materials-page 2

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
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